Evidence-Driven LLM Agent Bypasses HLS Pipeline Failures with PMLC and RAG

Most LLM-based HLS repair systems are half-baked: they stop after compilation or C simulation, feed raw tool logs into the model, and pray. That brittle approach dies the moment you hit a C/RTL co-simulation mismatch or a synthesis crash. A new paper from the team behind arXiv:2606.28409 finally treats C-to-HLS-C conversion as what it is—a closed-loop generation-verification-diagnosis-repair problem, with strict evidence isolation across Xilinx Vitis’s full four-stage pipeline.

Three Components That Make This Work

The workflow breaks into cooperating agents that loop until all four stages pass. First, a Progressive Mismatch Localization Chain (PMLC) takes a failed CSim or CoSim log, normalizes it, runs backward AST slicing on the source, and inserts instrumentation probes into the dual-trace (C and RTL) simulation output. That’s not magic—it’s structured debugging that produces localizable mismatch locations instead of a wall of compiler vomit.

Second, a typed-query, two-stage evidence RAG pulls from a self-evolving, family-routed repair-card pool. Cards are organized by HLS design family (control-heavy vs datapath-heavy, loop vs pipeline, etc.) and each card records the exact mismatch pattern, the fix applied, and the verification outcome. The RAG layer answers two query types: “what fix worked for this log pattern?” and “what instrumentation points reveal the mismatch?” This is not a generic vector store—it’s a curated, versioned repair memory that grows with every successful run.

Concrete Results That Move the Needle

Experimental comparisons against several unnamed “comparable state-of-the-art models” show the evidence-driven agent substantially outperforming on the full pipeline. The abstract doesn’t cite percentages, but the claim is clear: by closing the loop through all four Vitis stages (compilation, CSim, synthesis, CoSim), the agent catches mismatches that single-stage or raw-log-feed systems miss. The PMLC alone explains why: raw logs don’t point at the offending line; AST backward slicing and dual-trace instrumentation do.

What This Enables

This architecture turns HLS toolchain repair from a manual, trial-and-error slog into an automated, memory-augmented process. The repair-card pool learns over time—each new design family seeds a routing tree that makes future conversions faster. Next up: extending PMLC to other HLS tools (Intel oneAPI, AMD Vitis) and to multi-clock designs where timing mismatches explode. For now, anyone struggling with FPGA acceleration of C algorithms finally has an LLM pipeline that doesn’t go blind at the first CoSim failure.

Source: Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification
Domain: arxiv.org