FeFET 4T Bit-Cell Hits 0.13 μW Store Power, Skips Backup-Restore

0.13 microwatts of store power and a 2 nanosecond store time, with no explicit backup/restore operation - that's what a 4-transistor FeFET bit-cell delivers in non-volatile mode. This differential cell uses two cross-coupled ferroelectric field-effect transistors (FeFETs) and two access transistors, giving a 4T structure that is physically smaller than a conventional 6T SRAM cell and many prior nvSRAM designs.

4T Beats 6T: Smaller Footprint, Dual-Mode Operation

Prior nvSRAM cells that glue SRAM to eNVM devices (like RRAM or MRAM) require backup and restore (B&R) cycles, which add latency and energy overhead, and they usually inflate cell area. This design sidesteps those tradeoffs entirely. The cross-coupled FeFET pair acts as both the storage element and the sense amplifier, so the cell can be configured as a volatile SRAM or a non-volatile memory by adjusting write conditions. No explicit B&R means lower dynamic energy and simpler control logic.

Numbers That Matter: 0.13 μW and 2 ns Store

In non-volatile mode, the cell stores data in 2 ns while consuming just 0.13 μW of store power - numbers that are competitive with dedicated eNVM technologies. Because the FeFETs retain polarization without power, the cell holds its state after power loss. The abstract also notes the bit-cell can be viewed as a cross-coupled gain cell, opening up analog or compute-in-memory applications beyond pure storage.

What This Enables Next

The 4T FeFET bit-cell directly attacks the two biggest pain points of nvSRAM: area bloat and B&R overhead. If the authors can demonstrate endurance and retention comparable to conventional FeFETs, this topology could replace 6T SRAM in low-power embedded systems and IoT nodes where both volatility and persistent storage are needed on the same die.

Source: A Novel FeFET Differential Bit-Cell With Hybrid Volatile and Non-Volatile Memory Modes
Domain: arxiv.org