MINT Accelerator Cuts FPGA CNN Energy by 82% Using Dynamic Precision

32.6% higher throughput and 82.1% better energy efficiency than a fixed INT8 baseline—on a Zynq-7020, no less. That’s what MINT delivers for VGG-16 by throwing out the conventional right-to-left arithmetic playbook.

Why Left-to-Right Arithmetic Matters for Hardware

Most digital arithmetic crunches bits from least significant to most. MINT flips the order: compute most-significant-digit first (MSDF), and once the partial result hits the required precision, stop. No wasted cycles on trailing bits that the application never needs. The core is an MSDF serial-parallel inner-product unit that uses redundant signed-digit representation to keep carry chains short and timing tight.

Greedy Search Picks the Right Precision Per Layer

MINT’s authors run a budget-constrained greedy search across all convolution layers, testing each from INT2 up to INT7. The optimizer selects the lowest precision per layer while keeping total accuracy loss within 2% of the INT8 baseline. Result: average 5.64 bits for VGG-16, 6.04 for ResNet-18. That’s a direct hit to memory bandwidth and multiplier energy.

Real Numbers on a Real FPGA

The design synthesizes on a Xilinx Zynq-7020 at 200 MHz. For VGG-16: 19.86 GOPS, 29.51 GOPS/W. For ResNet-18: 18.86 GOPS, 26.40 GOPS/W. Compared to a conventional INT8 implementation, that’s 32.6% and 26.0% higher throughput, and 82.10% and 62.90% higher energy efficiency—with only 1.81% and 1.96% accuracy drops. MINT also beats every prior FPGA CNN accelerator the paper lists on the same Zynq-7020 platform in terms of energy efficiency.

MINT proves that MSDF digit-serial arithmetic isn’t just a textbook curiosity—it’s a practical lever for squeezing more inference out of resource-constrained FPGAs. Don’t be surprised when this trick shows up in the next wave of low-power edge accelerators.

Source: MINT: Dynamic-Precision CNN Inference with MSDF Digit-Serial Arithmetic on FPGA
Domain: arxiv.org