SNNs on FPGAs Hit 34μs Inference via hls4ml Extension

34 microseconds per inference. That's the latency a dense quantised Spiking Neural Network achieves on a standard FPGA when deployed through the hls4ml extension the authors describe in arXiv:2606.10008. For anyone building real-time inference systems—trigger readout in particle physics, low-latency control loops, edge audio processing—that number means SNNs just became a practical option on hardware you already know how to program.

Why SNNs on FPGAs Matter

Spiking Neural Networks process information as discrete events over time, not as static tensors. That temporal property gives them natural advantages for low-latency tasks and event-driven sensors. But most deployment paths assume neuromorphic ASICs like Intel's Loihi or BrainChip's Akida, which aren't everywhere. FPGAs are. Every scientific experiment, every aerospace control box, every production line with real-time constraints already relies on them. The hls4ml team—already famous for deploying deep neural nets on FPGAs in CERN experiments—has now added a clock-driven SNN backend that fits directly into that world.

The hls4ml Extension in Practice

The extension takes a PyTorch-trained SNN and runs it through high-level synthesis to produce FPGA firmware. No separate toolchain, no exotic HDL. The paper walks through a dense quantised SNN trained on the Heidelberg Spiking Digits dataset, a standard temporal audio benchmark. After training, the model is exported, optimized via hls4ml's existing infrastructure, and synthesized. The reported 34μs inference latency includes the full feed-forward pass of the spiking dynamics. That's competitive with neuromorphic hardware while staying inside a conventional synchronous FPGA design flow.

Real Validation, Not Just Simulation

Too many FPGA neural network papers stop at HLS simulation numbers. These authors went further: they compared the generated design against software reference computations, ran HLS C simulation, ran HLS synthesis, exported the IP, and fed it into Vivado for full synthesis reports. Every step checks that the discrete spike behavior matches the PyTorch reference. That level of validation matters when you're putting this into a trigger system that runs for years without a reboot.

What this opens up is straightforward: any lab or team that already uses hls4ml for standard inference can now experiment with spiking models without buying purpose-built silicon. The next practical step is to see how far the latency drops when you move beyond dense SNNs into the sparser, event-driven architectures this hardware actually expects.

Source: Spiking Neural Network inference on FPGAs with hls4ml
Domain: arxiv.org