IBM's Vertical Nanostack Doubles Chip Density, Extends Moore's Law by a Decade

IBM stuffed 100 billion transistors onto a chip the size of a fingernail by stacking them in two layers, doubling the density of its 2021 state-of-the-art and proving vertical scaling can keep Moore's Law alive. That's not a paper exercise - the company says chips built with this design can do 50% more work in the same time and sip 70% less energy.

Why Vertically Stacked Transistors Beat Shrinking

Transistors hit a wall around 15 years ago: shrink them below a few dozen nanometers and quantum mechanics starts flipping bits you didn't ask to flip. So the industry stopped shrinking and started building up. IBM's new approach, called a nanostack, fabricates a second layer of transistors directly on top of the first, layer by layer like a cake. The channel inside each transistor uses three nanosheets each 15 atoms thick, spaced 9 nm apart. That gives you the density without the quantum headaches.

This isn't just another incremental node. Jay Gambetta, director of IBM Research, called it "a meaningful leap forward." Dan Hutcheson at TechInsights says it puts another ten to fifteen years on the roadmap. The industry agrees - Intel, Samsung, TSMC, and Imec are all investigating the same complementary field-effect transistor (CFET) architecture.

The Staggered Layer Trick and What It Unlocks

IBM's twist: the second layer's transistors don't sit directly above the first layer's. They're staggered, which simplifies wiring and avoids a lot of routing nightmares. That's different from AMD's 3D V-Cache or Huawei's LogicFolding, which bond pre-fabricated layers together. IBM's method gives more precise alignment - critical when each transistor is atom-scale.

Huiming Bu, IBM's VP of global semiconductor R&D, expects designers to deploy this in everything from GPUs to CPUs. The architecture is a general layout, not a specific product. IBM will partner with manufacturers to put it into production. Within a decade, Gambetta expects nanostacked chips to be common in data centers, slashing their energy bills.

The Thermal Budget Problem and Who Solved It

Building transistors on top of transistors creates a thermal problem: you can't melt the bottom layer while cooking the top one. The ceiling is 400 degrees Celsius for the second layer. IBM figured out how to stay under that, though they're keeping the details proprietary. Qing Cao's group at UIUC has demonstrated a junctionless transistor approach that keeps the second-layer processes below 200 degrees C by skipping doping - the hottest step. He calls IBM's work "transformative" because they did it on a full wafer with a state-of-the-art manufacturing line.

The real challenge is yield: if either layer fails, the whole chip is scrap. That pushes up cost. But for data-center-grade hardware, the performance and efficiency payoff justifies the complexity. "I'm interested in what's their killer application," says Cao. So am I.

Source: IBM has unveiled chip technology that could help extend Moore's Law another decade
Domain: technologyreview.com